Advances in semiconductor technology and especially in the areas of semiconductor memories have led to higher semiconductor chip density and complexity. This results in tight geometries which have associated therewith process control problems occasionally resulting in failures in bit cells of the array. The failure etiology is frequently column related (as opposed to row related) resulting in defective columns of bit cells. However, the failure of a single bit in a large memory array of, for example, 64,000 memory, cells still constitutes a failure of the entire device.
To increase yield in a semiconductor memory array, such techniques as redundancy and error detection/correction schemes have been utilized. Redundancy is especially suited for repetitive circuits such as memory arrays wherein a portion of the circuits, such as a column of memory cells, is repeated on the chip. At test, it is then only necessary to either open a laser type fuse to insert the redundant circuit for the defective circuit or activate an electronic switching interface to make the replacement. One type of redundant circuit is discussed in U.S. Pat. No. 4,598,388, issued July 1, 1986 and assigned to Texas Instruments Incorporated. Another device is disclosed in U.S. Pat. No. 4,471,472, issued to E. S. Young on Sept. 11, 1984 and assigned to Advanced Microdevices, Inc. Redundant circuits, however, require a defined amount of silicon surface area or "overhead" for implementation thereof. In addition, redundant circuits must be activated during the manufacturing phase with the redundancy provided therefor constrained within the limits of the redundant circuit. Partial redundancy works well only with Read/Write memories. Read Only Memories (ROM's) need 100% redundancy.
The second technique for increasing yield on a high density semiconductor memory array is to utilize an error detecting and correcting code. Such codes usually contain two kinds of digits: information or message digits, and check or parity digits. Since the probability for the simultaneous appearance of two or more errors is much smaller than for single errors, attention is frequently focused on detecting and correcting only single bit errors. To implement an error detection/correction code, it is necessary not only to store the information digits but also to store corresponding parity information. The most widely used single error detecting code is the odd/even parity code, in which one parity bit is added to every code word. For the odd/even parity check, the additional bit is chosen so that the sum of all logic 1's and the data word, including this parity bit, is odd or even.
The odd/even parity error detecting code requires addition of an extra bit to each code word and is sometimes referred to as "horizontal" parity checking. If, however, the code words of a longer message are arranged in an array of n rows and m columns, then, besides the horizontal parity bit added to each row, another "vertical" parity bit may also be added to each column. This is referred to as a block parity error correcting code. The error can be detected either from the horizontal parity bit or from the vertical parity bit.
Another type of error correcting code is the Hamming code which is one of the more important single error detecting and correcting codes. This code cannot only detect and correct single error codes but can also detect double errors. Such devices have been developed for use external to a semiconductor memory. The data word output by the memory along with its parity information, is input to the error/detection circuit in order to detect if there is an error. If an error exists, this error is corrected and the corrected data word output therefrom. An error/detection circuit of this type is manufactured under the Part No. 2960 by Advanced Micro Devices. Examples of applications of other error detection/correction codes can be found in U.S. Pat. Nos. 4,479,214; 4,494,234; 4,497,058; 4,498,175; 4,506,365 and 4,468,769.
Although, error detection/correction codes provide the capability to correct single or multiple errors, integration of this capability into an integrated RAM presents some difficulties. It is necessary to both read corrected data from the memory and also generate the parity or check bits when writing data to the memory. The circuit overhead for this multiple Read/Write process can become cumbersome.